| Subject | Re: [RFC PATCH v2 11/27] x86/mm: Modify ptep_set_wrprotect and pmdp_set_wrprotect for _PAGE_DIRTY_SW | From | Dave Hansen <> | Date | Tue, 10 Jul 2018 15:44:32 -0700 |
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On 07/10/2018 03:26 PM, Yu-cheng Yu wrote: > + /* > + * On platforms before CET, other threads could race to > + * create a RO and _PAGE_DIRTY_HW PMD again. However, > + * on CET platforms, this is safe without a TLB flush. > + */
If I didn't work for Intel, I'd wonder what the heck CET is and what the heck it has to do with _PAGE_DIRTY_HW. I think we need a better comment than this. How about:
Some processors can _start_ a write, but end up seeing a read-only PTE by the time they get to getting the Dirty bit. In this case, they will set the Dirty bit, leaving a read-only, Dirty PTE which looks like a Shadow Stack PTE.
However, this behavior has been improved and will *not* occur on processors supporting Shadow Stacks. Without this guarantee, a transition to a non-present PTE and flush the TLB would be needed.
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