| From | Chen-Yu Tsai <> | Date | Thu, 28 Jun 2018 10:22:36 +0800 | Subject | Re: [PATCH v3 16/24] drm/sun4i: Enable DW HDMI PHY clock |
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On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec <jernej.skrabec@siol.net> wrote: > Current DW HDMI PHY code never prepares and enables PHY clock after it is > created. It's just used as it is. This may work in some cases, but it's > clearly wrong. Fix it by adding proper calls to enable/disable PHY > clock. > > Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant") > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
So why does it work on the H3? Because there's only one PLL that the whole display pipeline uses?
We should probably tag this for stable. So,
Cc: <stable@vger.kernel.org> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
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