Messages in this thread |  | | Subject | Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX() | From | Sinan Kaya <> | Date | Thu, 5 Apr 2018 21:34:31 -0400 |
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On 4/3/2018 8:55 AM, Sinan Kaya wrote: > While a barrier is present in writeX() function before the register write, > a similar barrier is missing in the readX() function after the register > read. This could allow memory accesses following readX() to observe > stale data. > > Signed-off-by: Sinan Kaya <okaya@codeaurora.org> > Reported-by: Arnd Bergmann <arnd@arndb.de> > --- > arch/mips/include/asm/io.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h > index fd00ddaf..6ac502f 100644 > --- a/arch/mips/include/asm/io.h > +++ b/arch/mips/include/asm/io.h > @@ -377,6 +377,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ > BUG(); \ > } \ > \ > + rmb(); \ > return pfx##ioswab##bwlq(__mem, __val); \ > } > >
Can we get these merged to 4.17?
There was a consensus to fix the architectures having API violation issues. https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html
-- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
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