Messages in this thread |  | | Subject | Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX() | From | Sinan Kaya <> | Date | Thu, 12 Apr 2018 18:20:16 -0400 |
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On 4/12/2018 5:51 PM, James Hogan wrote: > But why don't we always use wmb() in the writeX() case? Might not the > cached write to DMA buffer be reordered with the uncached write to MMIO > register from the coherent DMA point of view? I'm waiting on feedback > from MIPS hardware folk on this topic.
Are you asking about this?
#if defined(CONFIG_CPU_CAVIUM_OCTEON) || defined(CONFIG_LOONGSON3_ENHANCEMENT) #define war_io_reorder_wmb() wmb() #else -#define war_io_reorder_wmb() do { } while (0) +#define war_io_reorder_wmb() barrier() #endif
There is a write barrier in writeX() but seem to be different from platform to platform.
I'm not familiar with the MIPS architecture. We can always use a wmb() but it could hurt performance where it is not needed.
This is the kind of input we need from the MIPS folks if compiler barrier is enough or we need a wmb() for all cases.
-- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
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