Messages in this thread Patch in this message | | | Date | Wed, 14 Nov 2018 11:46:51 +0100 | From | Boris Brezillon <> | Subject | Re: [PATCH v5 3/9] spi: Add a driver for the Freescale/NXP QuadSPI controller |
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On Wed, 14 Nov 2018 10:43:00 +0000 Yogesh Narayan Gaur <yogeshnarayan.gaur@nxp.com> wrote:
> Hi Frieder, > > [..] > > > > > > Ok, I will have a look at what could make the chip selection fail in > > > case of AHB read. > > > > Could you try with this change applied: > > > > @@ -503,7 +503,7 @@ static void fsl_qspi_select_mem(struct fsl_qspi *q, struct > > spi_device *spi) > > map_addr = q->memmap_phy; > > else > > map_addr = q->memmap_phy + > > - 2 * q->devtype_data->ahb_buf_size; > > + q->devtype_data->ahb_buf_size; > > > > qspi_writel(q, map_addr, q->iobase + QUADSPI_SFA1AD + > > (i * 4)); > > } > > > > I have tried above change and also have done few more changes but still AHB read for CS1 is falling.
Have plugged a scope on the CS1 line, to make sure it's properly asserted when the memory is accessed?
> > I guess we need to implement dynamic memory mapping [1] for AHB Read as was being done in previous driver implementation. > Would try this and update you.
Sorry but I don't see why it would solve the problem we have here, but if it does, I'd like to have a clear explanation ;-).
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