Messages in this thread Patch in this message | | | Subject | Re: [RESEND PATCH V2 3/4] perf/x86/intel: drain PEBS buffer in event read | From | "Liang, Kan" <> | Date | Tue, 16 Jan 2018 13:49:13 -0500 |
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On 1/11/2018 10:45 AM, Jiri Olsa wrote: > On Thu, Jan 11, 2018 at 10:21:25AM -0500, Liang, Kan wrote: > > SNIP > >>> >>> hum, but the PEBS drain is specific just for >>> PERF_X86_EVENT_AUTO_RELOAD events, right? >> >> Accurately, PEBS drain is specific for PERF_X86_EVENT_FREERUNNING here. >> PERF_X86_EVENT_FREERUNNING event must be _AUTO_RELOAD event. >> But in some cases, _AUTO_RELOAD event cannot be _FREERUNNING event. >> >> Only the event which is both _FREERUNNING and _AUTO_RELOAD need to do PEBS >> drain in _read(). >> >> So it does the check in intel_pmu_pebs_read() >> + if (pebs_needs_sched_cb(cpuc)) >> + return intel_pmu_drain_pebs_buffer(); >> >>> >>> wrt readability maybe you could add function like: >> >> The existing function pebs_needs_sched_cb() can do the check. >> We just need to expose it, and also the intel_pmu_drain_pebs_buffer(). >> >> But to be honest, I still cannot see a reason for that. >> It could save a call to intel_pmu_pebs_read(), but _read() is not critical >> path. It doesn't save much. > > hum, pmu->read is also called for PERF_SAMPLE_READ for sample, > check perf_output_read > > for non sampling event you shouldn't be able to create PEBS > event, there's check in x86_pmu_hw_config > > I agree it does not save much, it just confused me while > I was reading the code, like why is this needed for all > events with precise_ip >
Sorry for the late response.
How about the patch as below? The patch will be split into two patches in V3. One is to introduce intel_pmu_large_pebs_read, the other is to introduce intel_pmu_read_event.
Thanks, Kan
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 731153a..1610a9d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2060,6 +2060,14 @@ static void intel_pmu_del_event(struct perf_event *event) intel_pmu_pebs_del(event); }
+static void intel_pmu_read_event(struct perf_event *event) +{ + if (intel_pmu_large_pebs_read(event)) + return; + + x86_perf_event_update(event); +} + static void intel_pmu_enable_fixed(struct hw_perf_event *hwc) { int idx = hwc->idx - INTEL_PMC_IDX_FIXED; @@ -3495,6 +3503,7 @@ static __initconst const struct x86_pmu intel_pmu = { .disable = intel_pmu_disable_event, .add = intel_pmu_add_event, .del = intel_pmu_del_event, + .read = intel_pmu_read_event, .hw_config = intel_pmu_hw_config, .schedule_events = x86_schedule_events, .eventsel = MSR_ARCH_PERFMON_EVENTSEL0, diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index a1edd91..3f11ede 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -978,6 +978,19 @@ void intel_pmu_pebs_del(struct perf_event *event) pebs_update_state(needed_cb, cpuc, event->ctx->pmu); }
+int intel_pmu_large_pebs_read(struct perf_event *event) +{ + struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); + + /* Check if the event has large pebs */ + if (!pebs_needs_sched_cb(cpuc)) + return 0 + + intel_pmu_drain_pebs_buffer(); + + return 1; +} + void intel_pmu_pebs_disable(struct perf_event *event) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 805400b..7d3cd32 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -923,6 +923,8 @@ void intel_pmu_pebs_disable_all(void);
void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
+int intel_pmu_large_pebs_read(struct perf_event *event); + void intel_ds_init(void);
void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
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