Messages in this thread Patch in this message | | | From | kan.liang@intel ... | Subject | [PATCH V5 2/8] perf/x86/intel/uncore: correct fixed counter index check for NHM | Date | Mon, 15 Jan 2018 10:57:03 -0800 |
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From: Kan Liang <Kan.liang@intel.com>
For Nehalem and Westmere, there is only one fixed counter for W-Box. There is no index which is bigger than UNCORE_PMC_IDX_FIXED. It is not correct to use >= to check fixed counter. The code quality issue will bring problem when new counter index is introduced.
Signed-off-by: Kan Liang <Kan.liang@intel.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> ---
Change since V4: - Add reviewed-by
arch/x86/events/intel/uncore_nhmex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/uncore_nhmex.c b/arch/x86/events/intel/uncore_nhmex.c index 93e7a83..173e267 100644 --- a/arch/x86/events/intel/uncore_nhmex.c +++ b/arch/x86/events/intel/uncore_nhmex.c @@ -246,7 +246,7 @@ static void nhmex_uncore_msr_enable_event(struct intel_uncore_box *box, struct p { struct hw_perf_event *hwc = &event->hw; - if (hwc->idx >= UNCORE_PMC_IDX_FIXED) + if (hwc->idx == UNCORE_PMC_IDX_FIXED) wrmsrl(hwc->config_base, NHMEX_PMON_CTL_EN_BIT0); else if (box->pmu->type->event_mask & NHMEX_PMON_CTL_EN_BIT0) wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); -- 2.7.4
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