Messages in this thread Patch in this message | | | From | Huacai Chen <> | Subject | [PATCH V4 2/3] mm: dmapool: Align to ARCH_DMA_MINALIGN in non-coherent DMA mode | Date | Fri, 15 Sep 2017 11:00:54 +0800 |
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In non-coherent DMA mode, kernel uses cache flushing operations to maintain I/O coherency, so the dmapool objects should be aligned to ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least on MIPS:
Step 1, dma_map_single Step 2, cache_invalidate (no writeback) Step 3, dma_from_device Step 4, dma_unmap_single
If a DMA buffer and a kernel structure share a same cache line, and if the kernel structure has dirty data, cache_invalidate (no writeback) will cause data lost.
Cc: stable@vger.kernel.org Signed-off-by: Huacai Chen <chenhc@lemote.com> --- mm/dmapool.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/mm/dmapool.c b/mm/dmapool.c index 4d90a64..2ac6f4a 100644 --- a/mm/dmapool.c +++ b/mm/dmapool.c @@ -140,6 +140,9 @@ struct dma_pool *dma_pool_create(const char *name, struct device *dev, else if (align & (align - 1)) return NULL; + if (!plat_device_is_coherent(dev)) + align = max_t(size_t, align, dma_get_cache_alignment()); + if (size == 0) return NULL; else if (size < 4) -- 2.7.0
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