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Subject[PATCH V4 0/2] measure SMI cost (kernel)
Date
From: Kan Liang <Kan.liang@intel.com>

Currently, there is no way to measure the time cost in System management
mode (SMM) by perf.

Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets,
the PMU core counters will freeze on SMI handler. But it will not have an
effect on free running counters. E.g. APERF counter.
The cost of SMI can be measured by (aperf - cycles).

A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set
FREEZE_WHILE_SMM bit in IA32_DEBUGCTL.

A new --smi-cost mode in perf stat is implemented to measure the SMI cost
by calculating cycles and aperf results. In practice, the percentages of
SMI cycles should be more useful than absolute value. So the output will be
the percentage of SMI cycles and SMI#.
If user wants to get the actual cycles, they can apply --no-metric-only.

Here is an example output.

Performance counter stats for 'sudo echo ':

SMI cycles% SMI#
0.1% 1

0.010858678 seconds time elapsed

Changes since V1:
- Only include kernel patch
- New functions to set msr bit on cpu and cpus.
Using the new functions to replace rdmsrl_on_cpu and wrmsrl_on_cpu.
That avoids the extra IPIs and atomic issue.
- Support hotplug

Changes since V2:
- reuse msr_info

Changes since V3:
- Add hotplug protection
- Thanks to Thomas's suggestion. Using msr_flip_bit interfaces to
replace msr_set/clear_on_cpu(s) interfaces.
- Serialize the entire setting of freeze_on_smi

Kan Liang (2):
x86/msr: expose msr_flip_bit function
perf/x86: add sysfs entry to freeze counter on SMI

arch/x86/events/core.c | 10 +++++++
arch/x86/events/intel/core.c | 60 ++++++++++++++++++++++++++++++++++++++++
arch/x86/events/perf_event.h | 3 ++
arch/x86/include/asm/msr-index.h | 2 ++
arch/x86/include/asm/msr.h | 1 +
arch/x86/lib/msr.c | 7 +++--
6 files changed, 80 insertions(+), 3 deletions(-)

--
2.7.4

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