Messages in this thread | | | Date | Tue, 13 Dec 2016 16:44:51 +0100 | From | Maxime Ripard <> | Subject | Re: [PATCH 2/6] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 |
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On Tue, Dec 13, 2016 at 11:22:48PM +0800, Icenowy Zheng wrote: > The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to > be changeable by changing the rate of PLL_CPUX. > > Add CLK_SET_RATE_PARENT flag to this clock. > > Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Thanks! Maxime
-- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com [unhandled content-type:application/pgp-signature] | |