Messages in this thread | | | Date | Mon, 14 Sep 2015 14:40:09 -0400 | From | Waiman Long <> | Subject | Re: [PATCH v6 1/6] locking/qspinlock: relaxes cmpxchg & xchg ops in native code |
| |
On 09/14/2015 08:06 AM, Peter Zijlstra wrote: > On Fri, Sep 11, 2015 at 03:27:44PM -0700, Davidlohr Bueso wrote: >> On Fri, 11 Sep 2015, Waiman Long wrote: >> >>> @@ -46,7 +46,7 @@ static inline bool virt_queued_spin_lock(struct qspinlock *lock) >>> if (!static_cpu_has(X86_FEATURE_HYPERVISOR)) >>> return false; >>> >>> - while (atomic_cmpxchg(&lock->val, 0, _Q_LOCKED_VAL) != 0) >>> + while (atomic_cmpxchg_acquire(&lock->val, 0, _Q_LOCKED_VAL) != 0) >>> cpu_relax(); >> This code has changed with Peter's recent ccas fix. And the whole virt_queued_spin_lock() >> thing will now be under pv configs. So this doesn't apply to native code anymore, so it >> looks like it should be dropped altogether. > Yeah, it also doesn't make sense, this ix x86 arch code, x86 cannot do > cmpxchg_acquire. Then again, I suppose we could argue its of > documentation value..
Yes, it is to be consistent with the change in asm_generic qspinlock.h. We can certainly skip that.
Cheers, Longman
| |