Messages in this thread | | | Date | Tue, 5 May 2015 13:39:03 -0500 | From | Aravind Gopalakrishnan <> | Subject | Re: [PATCH 2/4] x86/mce/amd: Introduce deferred error interrupt handler |
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On 5/4/2015 1:46 PM, Borislav Petkov wrote: > So you can use mce_read_aux(), yeah, you can move it to mce-internal.h
Re-using mce_read_aux() was not as trivial as I initially thought. The MISC address value we read in amd_threshold_interrupt() could also be the value in MSR0xc0000408 or MSR0xc0000409 (for a bank == 4 case). But in mce_read_aux(), we will only look at MSR_IA32_MCx_MISC(i) (which is 0x413 for bank = 4)
So, instead of mucking around with mce_read_aux(), I am reusing the 'misc' value from amd_threshold_interrupt() and just adding rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr)
> So you can pass a parameter to __log_error(..., threshold=true, misc) > and do > > if (threshold) > m.misc = misc; >
Here's how I have it currently- static void __log_error(unsigned int bank, bool is_thr, u64 misc) { struct mce m;
mce_setup(&m); rdmsrl(MSR_IA32_MCx_STATUS(bank), m.status); if (!(m.status & MCI_STATUS_VAL)) return;
if (is_thr) m.misc = misc;
m.bank = bank; rdmsrl(MSR_IA32_MCx_ADDR(bank), m.addr); mce_log(&m);
wrmsrl(MSR_IA32_MCx_STATUS(bank), 0); }
and works fine..
Before patch:
[76916.275587] [Hardware Error]: Corrected error, no action required. [76916.279576] [Hardware Error]: CPU:0 (15:60:0) MC0_STATUS[-|CE|-|-|AddrV|-|-|CECC]: 0x840041000028017b [76916.279576] [Hardware Error]: MC0 Error Address: 0x0000000000000000
Corrected error output: [ 102.623490] [Hardware Error]: Corrected error, no action required. [ 102.623668] [Hardware Error]: CPU:0 (15:60:0) MC0_STATUS[-|CE|-|-|AddrV|-|-|CECC]: 0x840041000028017b [ 102.623930] [Hardware Error]: MC0 Error Address: 0x00001f808f0ff040
Thanks, -Aravind.
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