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    SubjectRe: [PATCH] x86: Align jump targets to 1 byte boundaries
    On 04/10/2015 03:19 PM, Borislav Petkov wrote:
    > On Fri, Apr 10, 2015 at 02:08:46PM +0200, Ingo Molnar wrote:
    >> Now, the usual justification for jump target alignment is the
    >> following: with 16 byte instruction-cache cacheline sizes, if a
    > You mean 64 bytes?
    > Cacheline size on modern x86 is 64 bytes. The 16 alignment is probably
    > some branch predictor stride thing.

    IIRC it's a maximum decode bandwidth. Decoders on the most powerful
    x86 CPUs, both Intel and AMD, attempt to decode in one cycle
    up to four instructions. For this they fetch up to 16 bytes.
    If cacheline ends before 16 bytes are available, then decode
    will operate on fewer bytes, or it will wait for next cacheline
    to be fetched.

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