Messages in this thread | | | Date | Mon, 19 Oct 2015 18:24:23 +0200 | From | Peter Zijlstra <> | Subject | Re: Q: schedule() and implied barriers on arm64 |
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On Mon, Oct 19, 2015 at 04:21:08PM +0100, Catalin Marinas wrote: > On Mon, Oct 19, 2015 at 09:06:05AM +0200, Ingo Molnar wrote: > > * Peter Zijlstra <peterz@infradead.org> wrote: > > > > > In any case, its all moot now, since Paul no longer requires schedule() to imply > > > a full barrier. > > > > > > [...] > > > > Nevertheless from a least-surprise POV it might be worth guaranteeing it, because > > I bet there's tons of code that assumes that schedule() is a heavy operation and > > it's such an easy mistake to make. Since we are so close to having that guarantee, > > we might as well codify it? > > FWIW, the arm64 __switch_to() has a heavy barrier (DSB) but the reason > for this was to cope with potentially interrupted cache or TLB > maintenance (which require a DSB on the same CPU) and thread migration > to another CPU.
Right, but there's a path through schedule() that does not pass through __switch_to(); when we pick the current task as the most eligible task and next == prev.
In that case there really only is the wmb, a spin lock, an atomic op and a spin unlock (and a whole bunch of 'normal' code of course).
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