Messages in this thread | | | Date | Mon, 3 Feb 2014 13:37:11 -0600 | From | Aravind Gopalakrishnan <> | Subject | Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors |
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On 2/3/2014 1:32 PM, Borislav Petkov wrote: > On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote: >> On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: >>> The current logic that returns (sys_addr >> 8) & 0x7 when >>> num_dcts_intlv = 4 is incorrect. We should really be doing- >>> If intlv_addr = 0x4, then interleave on bits [9:8] and if >>> intlv_addr = 0x5, interleave on bits [10:9]. >>> >>> Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low) >>> (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf) >>> >>> Tested on F15 M30h with mce_inj module and patch did not cause >>> any regressions. >>> >>> Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> >>> --- >>> >> Ping.. > I haven't forgotten you - it's just that I'm not taking any patches > during the merge window. yes, I realised :) Just noticed rc1 on kernel.org; hence the ping..
Thanks in advance -Aravind.
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