Messages in this thread Patch in this message | | | From | Aravind Gopalakrishnan <> | Subject | [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors | Date | Tue, 21 Jan 2014 15:03:36 -0600 |
| |
The current logic that returns (sys_addr >> 8) & 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9].
Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low) (Link:http://support.amd.com/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf)
Tested on F15 M30h with mce_inj module and patch did not cause any regressions.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> --- drivers/edac/amd64_edac.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index b53d0de..ef9fe30 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -1240,9 +1240,17 @@ static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr, if (num_dcts_intlv == 2) { select = (sys_addr >> 8) & 0x3; channel = select ? 0x3 : 0; - } else if (num_dcts_intlv == 4) - channel = (sys_addr >> 8) & 0x7; - + } else if (num_dcts_intlv == 4) { + u8 intlv_addr = dct_sel_interleave_addr(pvt); + switch (intlv_addr) { + case 0x4: + channel = (sys_addr >> 8) & 0x3; + break; + case 0x5: + channel = (sys_addr >> 9) & 0x3; + break; + } + } return channel; } -- 1.7.10.4
| |