Messages in this thread Patch in this message | | | From | Aravind Gopalakrishnan <> | Subject | [PATCH 1/3] x86,amd: Refactor amd cpu topology functions for multi-node processors | Date | Mon, 22 Dec 2014 14:10:10 -0600 |
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We would like to be able to provide a mechanism for finding the NBC for each node in multi-node platforms. For this, we will need the number of nodes per processor.
So, factor this calculation out of amd_get_topology() and provide separate getter function 'amd_get_nbc_for_node' for obtaining NBC for a node.
Another useful calculation is to find the NBC of a node on which a given cpu is on. Provide a getter for this as well. - We are using it in EDAC drivers, MCE handlers right away, so marked extern. - We currently don't use amd_get_nbc_for_node outside of here, so marking it static. We can make this extern as and when need arises.
While at it, reverse the return condition in amd_get_topology and save an indent level.
Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> --- arch/x86/include/asm/processor.h | 1 + arch/x86/kernel/cpu/amd.c | 78 ++++++++++++++++++++++++++++++++-------- 2 files changed, 65 insertions(+), 14 deletions(-)
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h index a092a0c..6e1dc06 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -979,6 +979,7 @@ static inline int mpx_disable_management(struct task_struct *tsk) #endif /* CONFIG_X86_INTEL_MPX */ extern u16 amd_get_nb_id(int cpu); +extern unsigned int amd_get_nbc_for_cpu(int cpu); static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves) { diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index a220239..0c0eae5 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -281,6 +281,28 @@ static int nearby_node(int apicid) } #endif +#ifdef CONFIG_X86_HT +static u32 amd_get_num_nodes(struct cpuinfo_x86 *c) +{ + u32 nodes = 1; + + if (cpu_has_topoext) { + u32 ecx; + + ecx = cpuid_ecx(0x8000001e); + nodes = ((ecx >> 8) & 7) + 1; + } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { + u64 value; + + rdmsrl(MSR_FAM10H_NODE_ID, value); + nodes = ((value >> 3) & 7) + 1; + } + + return nodes; +} +EXPORT_SYMBOL_GPL(amd_get_num_nodes); +#endif + /* * Fixup core topology information for * (1) AMD multi-node processors @@ -291,15 +313,18 @@ static int nearby_node(int apicid) static void amd_get_topology(struct cpuinfo_x86 *c) { u32 nodes, cores_per_cu = 1; + u32 cores_per_node; + u32 cus_per_node; u8 node_id; int cpu = smp_processor_id(); /* get information required for multi-node processors */ + nodes = amd_get_num_nodes(c); + if (cpu_has_topoext) { u32 eax, ebx, ecx, edx; cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); - nodes = ((ecx >> 8) & 7) + 1; node_id = ecx & 7; /* get compute unit information */ @@ -310,27 +335,24 @@ static void amd_get_topology(struct cpuinfo_x86 *c) u64 value; rdmsrl(MSR_FAM10H_NODE_ID, value); - nodes = ((value >> 3) & 7) + 1; node_id = value & 7; } else return; /* fixup multi-node processor information */ - if (nodes > 1) { - u32 cores_per_node; - u32 cus_per_node; + if (nodes < 2) + return; - set_cpu_cap(c, X86_FEATURE_AMD_DCM); - cores_per_node = c->x86_max_cores / nodes; - cus_per_node = cores_per_node / cores_per_cu; + set_cpu_cap(c, X86_FEATURE_AMD_DCM); + cores_per_node = c->x86_max_cores / nodes; + cus_per_node = cores_per_node / cores_per_cu; - /* store NodeID, use llc_shared_map to store sibling info */ - per_cpu(cpu_llc_id, cpu) = node_id; + /* store NodeID, use llc_shared_map to store sibling info */ + per_cpu(cpu_llc_id, cpu) = node_id; - /* core id has to be in the [0 .. cores_per_node - 1] range */ - c->cpu_core_id %= cores_per_node; - c->compute_unit_id %= cus_per_node; - } + /* core id has to be in the [0 .. cores_per_node - 1] range */ + c->cpu_core_id %= cores_per_node; + c->compute_unit_id %= cus_per_node; } #endif @@ -365,6 +387,34 @@ u16 amd_get_nb_id(int cpu) } EXPORT_SYMBOL_GPL(amd_get_nb_id); +#ifdef CONFIG_X86_HT +static u32 amd_get_nbc_for_node(int node_id) +{ + struct cpuinfo_x86 *c = &boot_cpu_data; + u32 nodes, cores_per_node; + + nodes = amd_get_num_nodes(c); + cores_per_node = c->x86_max_cores / nodes; + + return cores_per_node * node_id; +} +EXPORT_SYMBOL_GPL(amd_get_nbc_for_node); +#endif + +#ifdef CONFIG_X86_HT +unsigned int amd_get_nbc_for_cpu(int cpu) +{ + unsigned int nbc = 0; + + /* for multi-node */ + if (test_cpu_cap(&boot_cpu_data, X86_FEATURE_AMD_DCM)) + nbc = amd_get_nbc_for_node(amd_get_nb_id(cpu)); + + return nbc; +} +EXPORT_SYMBOL_GPL(amd_get_nbc_for_cpu); +#endif + static void srat_detect_node(struct cpuinfo_x86 *c) { #ifdef CONFIG_NUMA -- 2.0.2
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