Messages in this thread | | | Date | Thu, 18 Dec 2014 16:07:53 +0100 | From | Lars-Peter Clausen <> | Subject | Re: [PATCH v3] sound/soc/adi/axi-spdif.c: Support programmable master clock |
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On 12/11/2014 08:44 AM, Mike Looijmans wrote: > If the master clock supports programmable rates, program it to generate > the desired frequency. Only apply constraints when the clock is fixed. > This allows proper clock generation for both 44100 and 48000 Hz based > sampling rates if the platform supports it. > > The clock frequency must be set before enabling it. Enabling the clock > was done in "startup", but that occurs before "hw_params" where the rate > is known. Enabling a programmable clock without first setting a valid > frequency may harm the system. Move the clock start to the hw_params > routine, and keep track of whether the clock has been started, because > shutdown may be called without having called hw_params first, and > hw_params may be called multiple times. > Starting the clock and enabling the SPDIF output AFTER programming the > dividers is a more logical order anyway. > > To detect if the source clock is fixed, the driver calls clk_round_rate > for two frequencies. If the results are equal, or if the call returns > an error, the driver assumes the clock is fixed. > > Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Acked-by: Lars-Peter Clausen <lars@metafoo.de>
Thanks.
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