Messages in this thread Patch in this message | | | From | Kever Yang <> | Subject | [PATCH v2 1/2] clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate | Date | Thu, 9 Oct 2014 21:50:29 -0700 |
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This patch add 400MHz and 500MHz to clock rate table for rk3288.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> ---
Changes in v2: - change the PLL setting of 400M to meet the constraints of TRM
drivers/clk/rockchip/clk-rk3288.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c index d053529..7c30a5a 100644 --- a/drivers/clk/rockchip/clk-rk3288.c +++ b/drivers/clk/rockchip/clk-rk3288.c @@ -86,8 +86,10 @@ struct rockchip_pll_rate_table rk3288_pll_rates[] = { RK3066_PLL_RATE( 594000000, 2, 198, 4), RK3066_PLL_RATE( 552000000, 1, 46, 2), RK3066_PLL_RATE( 504000000, 1, 84, 4), + RK3066_PLL_RATE( 500000000, 3, 125, 2), RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4), + RK3066_PLL_RATE( 400000000, 3, 100, 2), RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4), -- 1.9.1
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