Messages in this thread | | | From | Arnd Bergmann <> | Subject | Re: [PATCH 1/4] ARM: STi: add stid127 soc support | Date | Thu, 30 Jan 2014 19:35:16 +0100 |
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On Thursday 30 January 2014, Patrice CHOTARD wrote: > From: Alexandre TORGUE <alexandre.torgue@st.com> > > This patch adds support to STiD127 SoC. > The main adaptation is the L2 cache way size compare to STiH41x SoCs. > > Signed-off-by: alexandre torgue <alexandre.torgue@st.com> > Signed-off-by: Patrice Chotard <patrice.chotard@st.com> > --- > arch/arm/mach-sti/board-dt.c | 6 ++++++ > 1 file changed, 6 insertions(+)
Wouldn't it be better to read this value from the l2 cache controller node? I'd assume there might be more SoCs that will need a similar change, so it's better to come up with a solution that doesn't involve changing the kernel every time.
Arnd
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