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Subjectlinux-next: manual merge of the cortex tree with the arm tree
Hi Uwe,

Today's linux-next merge of the cortex tree got a conflict in
arch/arm/include/asm/cputype.h between commit 59530adc3f1b ("ARM: Define
CPU part numbers and implementors") from the arm tree and commit
6ebd4d038dbb ("ARM: stub out read_cpuid and read_cpuid_ext for
CPU_CP15=n") from the cortex tree.

I fixed it up (see below) and can carry the fix as necessary (no action
is required).

--
Cheers,
Stephen Rothwell sfr@canb.auug.org.au

diff --cc arch/arm/include/asm/cputype.h
index ad41ec2,574269e..0000000
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@@ -59,30 -60,25 +60,43 @@@ extern unsigned int processor_id
: "cc"); \
__val; \
})
- #else
- #define read_cpuid(reg) (processor_id)
- #define read_cpuid_ext(reg) 0
- #endif
+
+ #else /* ifdef CONFIG_CPU_CP15 */

+#define ARM_CPU_IMP_ARM 0x41
+#define ARM_CPU_IMP_INTEL 0x69
+
+#define ARM_CPU_PART_ARM1136 0xB360
+#define ARM_CPU_PART_ARM1156 0xB560
+#define ARM_CPU_PART_ARM1176 0xB760
+#define ARM_CPU_PART_ARM11MPCORE 0xB020
+#define ARM_CPU_PART_CORTEX_A8 0xC080
+#define ARM_CPU_PART_CORTEX_A9 0xC090
+#define ARM_CPU_PART_CORTEX_A5 0xC050
+#define ARM_CPU_PART_CORTEX_A15 0xC0F0
+#define ARM_CPU_PART_CORTEX_A7 0xC070
+
+#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
+#define ARM_CPU_XSCALE_ARCH_V1 0x2000
+#define ARM_CPU_XSCALE_ARCH_V2 0x4000
+#define ARM_CPU_XSCALE_ARCH_V3 0x6000
+
/*
+ * read_cpuid and read_cpuid_ext should only ever be called on machines that
+ * have cp15 so warn on other usages.
+ */
+ #define read_cpuid(reg) \
+ ({ \
+ WARN_ON_ONCE(1); \
+ 0; \
+ })
+
+ #define read_cpuid_ext(reg) read_cpuid(reg)
+
+ #endif /* ifdef CONFIG_CPU_CP15 / else */
+
+ #ifdef CONFIG_CPU_CP15
+ /*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
* rather than directly reading processor_id or read_cpuid() directly.
@@@ -92,21 -88,15 +106,30 @@@ static inline unsigned int __attribute_
return read_cpuid(CPUID_ID);
}

+ #else /* ifdef CONFIG_CPU_CP15 */
+
+ static inline unsigned int __attribute_const__ read_cpuid_id(void)
+ {
+ return processor_id;
+ }
+
+ #endif /* ifdef CONFIG_CPU_CP15 / else */
+
+static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
+{
+ return (read_cpuid_id() & 0xFF000000) >> 24;
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
+{
+ return read_cpuid_id() & 0xFFF0;
+}
+
+static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
+{
+ return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
+}
+
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
return read_cpuid(CPUID_CACHETYPE);
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