Messages in this thread | | | Subject | Re: [PATCH 1/1] perf, Add support for Xeon-Phi PMU | From | Peter Zijlstra <> | Date | Tue, 25 Sep 2012 13:32:38 +0200 |
| |
On Thu, 2012-09-20 at 13:03 -0400, Vince Weaver wrote: > One additional complication: some of the cache events map to > event "0". This causes problems because the generic events code > assumes "0" means not-available. I'm not sure the best way to address > that problem.
For all except P4 we could remap the 0 value to -2, that has all high bits set (like the -1) which aren't used by hardware.
P4 is stuffing two registers in the 64bit config space and actually has them all in use I think.. Cyrill?
| |