Messages in this thread | | | Subject | Re: [PATCH 3/4] perf, x86: check ucode before disabling PEBS on SandyBridge v3 | From | Peter Zijlstra <> | Date | Wed, 13 Jun 2012 23:36:57 +0200 |
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On Wed, 2012-06-13 at 14:34 -0700, Andi Kleen wrote: > > Stephane actually wrote: > > > > "Ok, so to close on this, I tried the 6/6/2012 ucode update on a few > > SNB-EP systems. > > > > I got two answers depending on the stepping: > > C1 (stepping 6) -> 0x618 > > C2 (stepping 7) -> 0x70c > > > > So we need to check x86_mask for stepping and adjust the value of > > snb_ucode_rev accordingly for model 45." > > not sure i understood your point? > What do you want me to change? > > I check different numbers on the different models. > > FWIW it works on a Sandy Bridge E and I believe I didn't change > the logic for non E, which Stephane tested.
Is there a ucode revision for C2 higher than 0x618 but lower than 0x70c ? If so, your code is wrong for it would enable PEBS on that chip.
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