Messages in this thread | | | From | Jacob Shin <> | Subject | [PATCH 0/4] perf, amd: Enable AMD family 15h northbridge counters | Date | Fri, 9 Nov 2012 19:01:34 -0600 |
| |
The following patchset enables 4 additional performance counters in AMD family 15h processors that counts northbridge events -- such as DRAM accesses.
This patchset is based on previous work done by Robert Richter <rric@kernel.org> :
https://lkml.org/lkml/2012/6/19/324
The main differences are:
- The northbridge counters are indexed contiguously right above the core performance counters.
- MSR address offset calculations are moved to architecture specific files.
- Interrups are set up to be delivered only to a single core.
Jacob Shin (3): perf, amd: Refactor northbridge event constraints handler for code sharing perf, x86: Move MSR address offset calculation to architecture specific files perf, amd: Enable northbridge performance counters on AMD family 15h
Robert Richter (1): perf, amd: Simplify northbridge event constraints handler
arch/x86/include/asm/cpufeature.h | 2 + arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/perf_event.h | 6 + arch/x86/kernel/cpu/perf_event.h | 21 +-- arch/x86/kernel/cpu/perf_event_amd.c | 279 +++++++++++++++++++++++----------- 5 files changed, 207 insertions(+), 103 deletions(-)
-- 1.7.9.5
| |