| Subject | Re: [PATCH 16/34] perf, x86: Support weight samples for PEBS | From | Peter Zijlstra <> | Date | Tue, 23 Oct 2012 15:15:10 +0200 |
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On Thu, 2012-10-18 at 16:19 -0700, Andi Kleen wrote: > From: Andi Kleen <ak@linux.intel.com> > > When a weighted sample is requested, first try to report the TSX abort cost > on Haswell. If that is not available report the memory latency. This > allows profiling both by abort cost and by memory latencies. > > Memory latencies requires enabling a different PEBS mode (LL). > When both address and weight is requested address wins. > > The LL mode only works for memory related PEBS events, so add a > separate event constraint table for those. > > I only did this for Haswell for now, but it could be added > for several other Intel CPUs too by just adding the right > table for them.
This looks like it will interfere with Stephane's LL patches -- which should be out any day now ;-)
Stephane, any comments on how we should deal with all that?
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