Messages in this thread | | | From | Andi Kleen <> | Subject | Re: [PATCH RFC 2/2] [x86] Optimize copy_page by re-arranging instruction sequence and saving register | Date | Thu, 11 Oct 2012 06:40:52 -0700 |
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ling.ma@intel.com writes:
> From: Ma Ling <ling.ma@intel.com> > > Load and write operation occupy about 35% and 10% respectively > for most industry benchmarks. Fetched 16-aligned bytes code include > about 4 instructions, implying 1.34(0.35 * 4) load, 0.4 write. > Modern CPU support 2 load and 1 write per cycle, so throughput from write is > bottleneck for memcpy or copy_page, and some slight CPU only support one mem > operation per cycle. So it is enough to issue one read and write instruction > per cycle, and we can save registers.
I don't think "saving registers" is a useful goal here.
> > In this patch we also re-arrange instruction sequence to improve performance > The performance on atom is improved about 11%, 9% on hot/cold-cache > case respectively.
That's great, but the question is what happened to the older CPUs that also this sequence. It may be safer to add a new variant for Atom, unless you can benchmark those too.
-Andi
-- ak@linux.intel.com -- Speaking for myself only
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