Messages in this thread | | | Date | Tue, 31 Jan 2012 16:27:41 +0900 | Subject | Re: [PATCH] amba-pl011: clear previous interrupts before request_irq | From | Chanho Min <> |
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> Sorry for late reply and missing sign-off. > In the setup where console is disabled and logs are diverted to buffer, it is > observed that, continuous uart interrupts are coming. Even before IMSC > (Interrupt mask set/clear register) is enabled for TX or RX interrupts, > it is seen that interrupt handler getting called just after request_irq. > It was found that this situation happens when RIS (raw interrupt register) > has some pending interrupts (e.g. RI, CTS, DCD, RX etc. but IMO RX is main) > when control gets transferred to kernel from bootloader. This refers that > GIC (global interrupt controller) is providing interrupt even if interrupts > for UART are masked/disabled in IMSC register. > In this state problem elivated when cpu is looping in interrupt handler > because of Rx interrupt set but Rx fifo is empty (hence rx_char is simply > returning). How UART goes in to this state is still not completely > understood. Hi, This is my analsys. RXFE is set by 'writew(0, uap->port.membase + uap->lcrh_rx)' UART can not get any data from DR because of the below break condtion. pl011_fifo_to_tty while (max_count--) { if (status & UART01x_FR_RXFE) break; Rx interrupt is never cleared. cpu is looping in ISR.
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