Messages in this thread | | | Date | Tue, 15 Feb 2011 11:01:21 +0000 | Subject | Re: [PATCH 0/2] jump label: 2.6.38 updates | From | Will Newton <> |
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On Mon, Feb 14, 2011 at 11:19 PM, H. Peter Anvin <hpa@zytor.com> wrote: > On 02/14/2011 02:37 PM, Matt Fleming wrote: >>> >>> I don't see how cache coherency can possibly work if the hardware >>> behaves this way. >> >> Cache coherency is still maintained provided writes/reads both go >> through the cache ;-) >> >> The problem is that for read-modify-write operations the arbitration >> logic that decides who "wins" and is allowed to actually perform the >> write, assuming two or more CPUs are competing for a single memory >> address, is not implemented in the cache controller, I think. I'm not a >> hardware engineer and I never understood how the arbitration logic >> worked but I'm guessing that's the reason that the ll/sc instructions >> bypass the cache. >> >> Which is why the atomic_t functions worked out really well for that >> arch, such that any accesses to an atomic_t * had to go through the >> wrapper functions. > > I'm sorry... this doesn't compute. Either reads can work normally (go > through the cache) in which case atomic_read() can simply be a read or > they don't, so I don't understand this at all.
The CPU in question has two sets of instructions:
load/store - these go via the cache (write through) ll/sc - these operate literally as if there is no cache (they do not hit on read or write)
This may or may not be a sensible way to architect a CPU, but I think it is possible to make it work. Making it work efficiently is more of a challenge. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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