Messages in this thread | | | Date | Tue, 15 Feb 2011 01:19:58 +0100 (CET) | Subject | Re: [PATCH 0/2] jump label: 2.6.38 updates | From | "Segher Boessenkool" <> |
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>> What CPU family are we talking about here? For cache coherent CPUs, >> cache coherence really is supposed to work, even for mixed atomic and >> non-atomic instructions to the same variable. > > I'm really curious to know which CPU families too. I've used git blame > to see where these lwz/stw instructions were added to powerpc, and it > points to: > > commit 9f0cbea0d8cc47801b853d3c61d0e17475b0cc89
> So let's ping the relevant people to see if there was any reason for > making these atomic read/set operations different from other > architectures in the first place.
lwz is a simple 32-bit load. On PowerPC, such a load is guaranteed to be atomic (except some unaligned cases). stw is similar, for stores. These are the normal insns, not ll/sc or anything.
At the time, volatile tricks were used to make the accesses atomic; this patch changed that. Result is (or should be!) better code generation.
Is there a problem with it?
Segher
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