Messages in this thread | | | Date | Tue, 11 Oct 2011 18:56:03 +0800 | Subject | Re: [Question] PM-QoS: PM_QOS_CPU_DMA_LATENCY == interrupt latency? | From | Ming Lei <> |
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On Tue, Oct 11, 2011 at 6:07 PM, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote: >> > No. Well it may be on some platforms but it isn't the same thing. On some >> > devices a DMA transfer doesn't need the CPU involved but needs the CPU to >> > respond within a set timescale (eg for coherency or bus arbitration). It >> >> I understand only the CPU can respond after it is notified by a >> interrupt event, don't I? > > The instruction stream being executed maybe, but not things like the cache > >> Also could you give a example about how the CPU responds to a DMA transfer >> within a set timescale if it is required? > > The kind of thing you are dealing with is > > DMA engine requests a cache line of data > CPU wakes out of sleep, completes bus transaction
I think the CPU should be woken up by interrupt from DMA engine, so it is still a kind of interrupt latency?
Also looks like it is a bit odd that why CPU is involved to complete the bus transaction which should have been done by DMA engine only. Is there a practical example about this?
> CPU goes back to sleep > DMA engine starts outputting data bits over SPI bus or similar > > repeat until done > > so it's not instruction level stuff, merely bus traffic. >
thanks, -- Ming Lei -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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