Messages in this thread | | | Date | Tue, 11 Oct 2011 09:28:54 +0800 | Subject | Re: [Question] PM-QoS: PM_QOS_CPU_DMA_LATENCY == interrupt latency? | From | Ming Lei <> |
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Hi,
On Tue, Oct 11, 2011 at 12:25 AM, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote: > On Mon, 10 Oct 2011 22:31:34 +0800 > Ming Lei <tom.leiming@gmail.com> wrote: > >> Hi, >> >> Looks like it is a bit difficult to understand PM_QOS_CPU_DMA_LATENCY >> from the words' meaning. >> >> After searching from google, I don't find some useful information about >> the root cause for introducing PM_QOS_CPU_DMA_LATENCY. I understand >> it is very similar to interrupt latency. Also from the comment for >> omap_pm_set_max_mpu_wakeup_lat in file[1], the description is basically same >> with interrupt latency. >> >> >From comments of pm_qos_add_request usages in drivers, it can be understood >> as interrupt latency too, IMO. >> >> So, could we think that PM_QOS_CPU_DMA_LATENCY is interrupt latency? > > No. Well it may be on some platforms but it isn't the same thing. On some > devices a DMA transfer doesn't need the CPU involved but needs the CPU to > respond within a set timescale (eg for coherency or bus arbitration). It
I understand only the CPU can respond after it is notified by a interrupt event, don't I?
Also could you give a example about how the CPU responds to a DMA transfer within a set timescale if it is required?
> is not the same thing as IRQ latency.
thanks, -- Ming Lei
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