Messages in this thread Patch in this message | | | Date | Tue, 29 Jun 2010 16:43:45 +0900 | Subject | [PATCH -next] tile: set ARCH_KMALLOC_MINALIGN | From | FUJITA Tomonori <> |
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The minimum alignment and width of DMA is L2_CACHE_BYTES (because your dma_get_cache_alignment() returns L2_CACHE_BYTES), right?
= From: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Subject: [PATCH -next] tile: set ARCH_KMALLOC_MINALIGN
Architectures that handle DMA-non-coherent memory need to set ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe: the buffer doesn't share a cache with the others.
Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> --- arch/tile/include/asm/cache.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h index ee59714..e08d9e8 100644 --- a/arch/tile/include/asm/cache.h +++ b/arch/tile/include/asm/cache.h @@ -31,6 +31,8 @@ #define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT) #define L2_CACHE_ALIGN(x) (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES) +#define ARCH_KMALLOC_MINALIGN L2_CACHE_BYTES + /* use the cache line size for the L2, which is where it counts */ #define SMP_CACHE_BYTES_SHIFT L2_CACHE_SHIFT #define SMP_CACHE_BYTES L2_CACHE_BYTES -- 1.6.5
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