Messages in this thread | ![/](/images/icornerl.gif) | | Date | Thu, 11 Nov 2010 10:54:05 -0800 | From | Yinghai Lu <> | Subject | Re: [PATCH -v2 2/2] x86/pci: Add mmconf range into e820 for when it is from MSR with amd faml0h |
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On 11/11/2010 12:50 AM, Jan Beulich wrote: >>>> On 11.11.10 at 01:54, Yinghai Lu <yinghai@kernel.org> wrote: >> @@ -191,10 +208,12 @@ void __cpuinit fam10h_check_enable_mmcfg >> /* only trust the one handle 256 buses, if acpi=off */ >> if (!acpi_pci_disabled || busnbits >= 8) { >> u64 base; >> - base = val & (0xffffULL << 32); >> + base = val & (FAM10H_MMIO_CONF_BASE_MASK << >> + FAM10H_MMIO_CONF_BASE_SHIFT); >> if (fam10h_pci_mmconf_base_status <= 0) { >> fam10h_pci_mmconf_base = base; >> fam10h_pci_mmconf_base_status = 1; >> + e820_add_mmconf_range(busnbits); >> return; >> } else if (fam10h_pci_mmconf_base == base) >> return; > > I don't think adding the range in this case is correct: Here, we > found that the BIOS enabled the feature, and we're doing > nothing to "correct" it, so we also should expect the range > to be reserved by the BIOS.
this function is protected by PCI_CHECK_ENABLE_AMD_MMCONF
void __cpuinit fam10h_check_enable_mmcfg(void) { u64 val; u32 address;
if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF)) return;
and could have systems that setting in hw config is right, but BIOS doesn't put them with e820 reserved entries.
Thanks
Yinghai
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