Messages in this thread | | | Date | Thu, 29 Jan 2009 10:35:06 +0000 | From | Russell King - ARM Linux <> | Subject | Re: [PATCH C 08/13] OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate |
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On Wed, Jan 28, 2009 at 12:08:32PM -0700, Paul Walmsley wrote: > When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use > the user's desired rate in clk->rate to determine whether to put the > DPLL into bypass or lock mode, rather than reading the DPLL's current > idle state from its hardware registers. > > This fixes a bug observed when leaving retention. Non-CORE DPLLs were > not being relocked when downstream clocks re-enabled; rather, the DPLL > entered bypass mode. > > Problem reported by Tero Kristo <tero.kristo@nokia.com>. > > linux-omap source commit is 8b1f0bd44fe490ec631230c8c040753a2bda8caa. > > Signed-off-by: Paul Walmsley <paul@pwsan.com> > Signed-off-by: Tony Lindgren <tony@atomide.com> > Cc: Tero Kristo <tero.kristo@nokia.com>
Patch 6 did it this way. Patch 7 changed it to use omap2_get_dpll_rate() and this patch changes it back. What's the point of submitting all this detail? It's just pure noise. Collapse these three patches into one please.
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