Messages in this thread Patch in this message | | | From | Paul Walmsley <> | Subject | [PATCH C 08/13] OMAP3 clock: put DPLL into bypass if bypass rate = clk->rate, not hardware rate | Date | Wed, 28 Jan 2009 12:08:32 -0700 |
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When a non-CORE DPLL is enabled via omap3_noncore_dpll_enable(), use the user's desired rate in clk->rate to determine whether to put the DPLL into bypass or lock mode, rather than reading the DPLL's current idle state from its hardware registers.
This fixes a bug observed when leaving retention. Non-CORE DPLLs were not being relocked when downstream clocks re-enabled; rather, the DPLL entered bypass mode.
Problem reported by Tero Kristo <tero.kristo@nokia.com>.
linux-omap source commit is 8b1f0bd44fe490ec631230c8c040753a2bda8caa.
Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Cc: Tero Kristo <tero.kristo@nokia.com> --- arch/arm/mach-omap2/clock34xx.c | 4 +--- 1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 844fe82..424eed6 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -280,9 +280,7 @@ static int omap3_noncore_dpll_enable(struct clk *clk) if (!dd) return -EINVAL; - rate = omap2_get_dpll_rate(clk); - - if (dd->bypass_clk->rate == rate) + if (clk->rate == dd->bypass_clk->rate) r = _omap3_noncore_dpll_bypass(clk); else r = _omap3_noncore_dpll_lock(clk);
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