Messages in this thread | | | Date | Sun, 14 Sep 2008 17:29:47 +0200 | From | Ingo Molnar <> | Subject | Re: [patch 0/7] x86, cpa: cpa related changes to be inline with TLB Application note |
| |
* Suresh Siddha <suresh.b.siddha@intel.com> wrote:
> TLB Application note[1] says: > > "The TLBs may contain both ordinary and large-page translations for a 4-KByte > range of linear addresses. This may occur if software modifies the paging > structures so that the page size used for the address range changes. If the > two translations differ with respect to page frame or attributes (e.g., > permissions), processor behavior is undefined and may be implementation > specific. The processor may use a page frame or attributes that correspond to > neither translation; it may improperly set or fail to set the dirty bit in the > appropriate paging-structure entry. > > Such undefined behavior is problematic because prefetches and memory accesses > that are a result of speculative execution may occur, using the affected range > of linear addresses. It is also problematic if software (including the software > modifying the paging structures) is accessing data or executing code in the > affected range of linear addresses. Software should not write to a > paging-structure entry in a way that would change, for any linear address, > both the page size and either the page frame or attributes." > > Currently we violate this at: > > a. kernel identity mapping, where large/small pages setup very early in the > boot will be split up/merged into large pages along with attribute changes > during the direct memory mapping init. > > b. while doing cpa(), potentially we will split large page and change attribute > both at the same time. > > Following patches fixes this behavior. > > [1] http://developer.intel.com/design/processor/applnots/317080.pdf > > Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
applied to tip/x86/pat, thanks Suresh.
Ingo
| |