Messages in this thread | | | Date | Fri, 13 Jun 2008 16:28:43 +0200 | From | Andreas Herrmann <> | Subject | Re: [patch 3/6] x86: use cpuinfo to check for interrupt pending message msr |
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On Fri, Jun 13, 2008 at 02:38:30PM +0200, Thomas Gleixner wrote: > On Fri, 13 Jun 2008, Andreas Herrmann wrote: > > > + /* Family 0x0f models < rev F do not have this MSR */ > > > + if (c->x86 == 0x0f && c->x86_model < 0x40) > > > + return 0; > > > > Just some minor nitpicking. > > Older AMD family 0xf CPUs have this Interrupt Pending Message > > Register. But they do not support C1E and thus bits 27 and 28 of this > > MSR are reserved. > > So the check can be simplified to always check the MSR for all > family >= 0x0f CPUs ?
First of all I thought of changing the comment.
But now that you ask: Documentation for older K8 CPUs says that reserved bits in that MSR are "Read as Zero". But otherwise it also says "Software must not depend on the state of a reserved field ..."
Maybe I am a little paranoid but I would keep the model check.
Andreas
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