Messages in this thread | | | Date | Fri, 7 Nov 2008 15:44:09 +0100 | From | "stephane eranian" <> | Subject | [PATCH] x86 debugctl MSR access interface |
| |
Hello,
On Intel X86 processors, the DEBUGCTL msr contains lots of bits to control various unrelated features, such as LBR, BTS, PMU.
Nowadays, several subsystems need access to this MSR to set or clear the bits they care about. In 2.6.27, the new DS/BTS interface was introduced and DEBUGCTL can now be cleared and restored on context switches.
The KPROBE interface also uses DEBUGCTL.
In the context of perfmon, it can be interesting to also modify bits in DEBUGCTL, such as FREEZE_PMU_ON_PMI but also the bits controlling the LBR (bit 0 and 11). With perfmon, however, there are situations, e.g. LBR, where the DEBUGCTL bits are managed on a per-CPU level and not per-task level. Simply overwriting DEBUGCTL on context switch may conflict with per-cpu usage.
It appears that modifications to DEBUGCTL must be done using a read-modify-write approach rather than pure write. To that extent, I would like to propose the attached patch which modifies the update_debugctlmsr() function to implement a read-modify-write access. The caller passes the value of debugctl and a mask of bits of interest. For instance, if you want to set bit 1 and clear bit 0, then you call update_debugctlmsr(0x2, 0x3).
Please let me know what you think about this patch.
Thanks. [unhandled content-type:application/octet-stream] | |