Messages in this thread | | | Date | Mon, 12 Mar 2007 06:35:09 +0200 | From | "Michael S. Tsirkin" <> | Subject | Re: SATA resume slowness, e1000 MSI warning |
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> Quoting Eric W. Biederman <ebiederm@xmission.com>: > Subject: Re: SATA resume slowness, e1000 MSI warning > > "Michael S. Tsirkin" <mst@mellanox.co.il> writes: > > > OK I guess. I gather we assume writing read-only registers has no side effects? > > Are there rumors circulating wrt to these? > > I haven't heard anything about that, and if we are writing the same value back > it should be pretty safe. > > I have heard it asserted that at least one version of the pci spec > only required 32bit accesses to be supported by the hardware. One of > these days I will have to look that and see if it is true.
Maybe. But surely before the PCI-X days.
> I do know > it can be weird for hardware developers to support multiple kinds of > decode.
Is this the only place where Linux uses pci_read_config_word/pci_read_config_dword? I think such hardware will be pretty much DOA on all OS-es. Why don't we wait and see whether someone reports a broken config?
> As I recall for pci and pci-x at the hardware level the only > difference in between 32bit transactions and smaller ones is the state > of the byte-enable lines.
True, and same holds for PCI-Express.
So let's assume hardware implements RO correctly but ignores the BE bits - nothing bad happens then, right?
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