Messages in this thread | ![/](/images/icornerl.gif) | | Subject | Re: Ordering between PCI config space writes and MMIO reads? | From | Roland Dreier <> | Date | Tue, 31 Oct 2006 14:30:13 -0800 |
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> I'm beginning to think Michael Tsirkin has the only solution to this > -- architectures need to check that their hardware blocks until the > config write completion has occurred (and if not, simulate that it has > in software).
OK, I guess I'm convinced. The vague language in the base PCI 3.0 spec about "dependencies" made me think that a read of a config register had to wait until all previous writes to the same register are done. So I'll drop this patch for now.
John, you'll need to try and come up with a way to solve this in the Altix implementation of pci_write_config_xxx().
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