Messages in this thread | | | Subject | RE: [PATCH] pci-mmconfig fix for 2.6.9 | Date | Fri, 12 Nov 2004 09:52:17 -0800 | From | "Michael Chan" <> |
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On Wednesday, November 10, 2004 11:58 PM Andi Kleen wrote: > Where is it guaranteed that these writes are non posted?
Intel chipset engineer confirmed that they are non-posted. Here are excerpts from some email exchange with Intel. We reported the out-of-spec dummy read problem to Intel a while back.
Begin forwarded message:
Hi Michael,
I have checked our chipset engineer. He specified that the mmconfig is truly non posted and memory cycles will be completed only after the config write are finished.
So I think flushing is not necessary and readl can be removed.
Thanks, Sundar
-----Original Message----- From: Michael Chan [mailto:mchan@broadcom.com] Sent: Friday, November 05, 2004 5:08 AM To: Durairaj, Sundarapandian Subject: RE: MMCONFIG Bug
Hi Sundar,
Thanks for the update. I agree that config cycles are non-posted and therefore flushing is unnecessary. However, since config cycles are not directly generated by the CPU, it is a bit more complicated. When the CPU issues the memory cycle (writel) to the chipset, the chipset will translate the memory cycle into a PCI Express config request on the appropriate PCI Express link. The target device will then return a completion.
Is the memory cycle to the chipset posted or not? In other words, does the chipset complete the memory cycle before issuing the config cycle, or does it issue the config cycle and wait for completion before completing the memory cycle (writel) from the CPU? If the latter is true, then it is unnecessary to flush the writel as it is truly non-posted. If the former is true, I think flushing is still necessary. Just wanted to confirm this.
Thanks, Michael
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