Messages in this thread | | | Date | Mon, 1 Sep 2003 06:58:04 +0100 | From | Jamie Lokier <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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Geert Uytterhoeven wrote: > Are you also interested in m68k? ;-) > > cassandra:/tmp# time ./test > Test separation: 4096 bytes: FAIL - store buffer not coherent
Especially! I hadn't expected to see any machine that would print "store buffer not coherent". It means that if there's an L1 cache, it is coherent, but any store-then-load bypass in the CPU pipeline is using the virtual address with no rollback after MMU translation.
I had thought it would only be the case with chips using an external MMU, but now that I think about it, the older simpler chips aren't going to bother with things like pipeline rollback wherever they can get away without it!
(The other CPU that is reporting "store buffer not coherent" is PA-RISC, which is even more of an eye opener. That has a big 1MiB coherent L1 cache, and the pipeline bypass is coherent for very large separations but not others!)
Thanks, -- Jamie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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