Messages in this thread | | | Date | Mon, 1 Sep 2003 02:58:23 +0100 | From | Jamie Lokier <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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Paul Mundt wrote: > On Mon, Sep 01, 2003 at 01:37:50AM +0100, Jamie Lokier wrote: > > > sh (VIPT cache): > > > > > > Test separation: 4096 bytes: FAIL - cache not coherent > > > Test separation: 8192 bytes: FAIL - cache not coherent > > > Test separation: 16384 bytes: pass > > > > A VIVT cache can do that, but I think a VIPT cache should always be coherent. > > Do I misunderstand? > > > There's nothing stating that VIPT == automatic coherency, > as is obviously the case for sh, where we are completely VIPT, but > are also non coherent.
Ah. A VIPT cache needn't be coherent with itself if isn't coherent w.r.t. external devices. Thanks.
-- Jamie
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