lkml.org 
[lkml]   [2003]   [Aug]   [29]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
SubjectRe: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this
From
Date
Jamie Lokier <jamie@shareable.org> writes:

> I already got a surprise (to me): my Athlon MP is much slower
> accessing multiple mappings which are within 32k of each other, than
> mappings which are further apart, although it is coherent. The L1

Most x86 and probably most other modern CPUs have virtually addressed L1 caches.
It's just too slow to wait for the MMU for an L1 access which is really critical.

So such artifacts are expected

> data cache is 64k. (The explanation is easy: virtually indexed,
> physically tagged cache moves data among cache lines, possibly via L2).

On x86 L2 is usually physically tagged.

Mostly only ARM,MIPS et.al. have virtually tagged L2.

-Andi
-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-03-22 13:48    [W:0.036 / U:0.176 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site