Messages in this thread | | | Date | Sun, 17 Aug 2003 22:52:45 +0000 | From | Philippe Elie <> | Subject | Re: about PENTIUM4 cache line |
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Jamie Lokier wrote: > michaelc wrote: > >> I read the Intel IA-32 developer's manual recently, and I found >> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes >> wide, but the thing make me confused is that the default value >> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's >> not 6? Any expanation about this would be appreciated! > > > I don't recall seeing an answer to this. > Was there one?
There is some confusion about P4 cache line size but
Intel Software Developer's Manual VOL 1
Page 2.12, Par 2.6: "128-byte cache line size - Two 64-byte sectors"
regards, Philippe Elie
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