Messages in this thread | | | Subject | Re: [PATCH][2.5][RFT] sfence wmb for K7,P3,VIAC3-2(?) | From | Andi Kleen <> | Date | 01 Apr 2003 13:49:32 +0200 |
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On Tue, 2003-04-01 at 13:28, Dave Jones wrote: > On Tue, Apr 01, 2003 at 12:11:00PM +0200, Andi Kleen wrote: > > sfence is part of SSE2. That's X86_SSE2 > > I'm not so sure this is correct. A quick google suggests > otherwise, and the C3 Nehemiah (which only supports SSE1) seems > to run sfence instructions just fine.
Yes, you're correct. It was SSE1, not SSE2.
The problem Zwane encountered is that early Athlons don't support SSE1, only XP+ do
To use it he would need an a new CONFIG split for Athlon XP and earlier Athlon. iirc it didn't make much difference on the athlon anyways which has quite fast locked operations on exclusive cachelines - sfence seems to be more useful on P4.
-Andi
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