Messages in this thread | | | Date | Wed, 15 Jan 2003 10:33:56 -0800 | Subject | process switch and page directory on INTEL ???? | From | Yang Yang <> |
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(please CC me on answers, I haven't been admitted into this list yet,thanks)
hi all: thank you for reading this, this has puzzled me for quite a time.
I read "INTEL architecture developers' manual", and became interested in how process / context switch ( called task switch in INTEL doc ) is done in linux, to me , looks like these happened: 1)an interupt gate ( for timer interupt ) directs flow to kernel mode for old process
2) kernel changes EIP,ESP and other registers, load new cr3 for new process
3) goes into USER mode for new process
my question is, a) for (1) to catch the interrupt, it must know the interrupt vector, so it must have an entry in its page directory and page table for the IDT, ( and similarly, GDT, TSS .... ) , because from intel doc, the IDTR ( and all other descriptor tables, registers except cr3 ) use *linear* address instead of physical. so , every process,and kernel thread must have a page table/directory mapping for the IDT,and that mapping maps to the same physical address ? same with GDT,TSS? if this is true, my thought is, in linux, it may well be that light weight process solves this----- sharing a page directory/table? but what with other OS'es ? they must provide a mapping of IDT for each process, because this is determined by hardware.
(b) from 1) to 2) , is the page table/directory changed at all? ( if changed, this might be called a "task gate" instead ) what paging system does the kernel use ?
thank you all
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