Messages in this thread | | | From | "Protasevich, Natalie" <> | Subject | RE: Question about xAPIC lowest priority delivery | Date | Mon, 13 Jan 2003 21:43:36 -0600 |
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>Anyway, is this a known erratum for xAPICs in parallel mode? (Namely, a bug
>in the XTPR arbitration logic in host bridges.) >For that matter, does this happen on non-Summit xAPIC boxes? Anyone out there >with a >= 2 CPU P4 box that uses parallel interrupts care to comment
I am not sure if we fall in the parallel mode category, but I will comment since I was also concerned about xTPR mechanism.
We use lowest priority delivery for xAPIC-APIC case the following way: set the destination to the logical id of boot CPU, set the LPDM bit on the destination (0x01XXXX). This way, if something is wrong with xTPR mechanism, the interrupt goes to boot CPU. (I presume it is about IA32 case, because it is different for Itanium). Then, I have to increase priority entering an interrupt by writing to the TPRI register, and lower it on the exit from it to make it available for the next one... Besides this, due to some erratum (I wish I had my specs here) I have to read from LDR and write back to it after changing TPRI value: apic_write_around(APIC_TASKPRI, pri); apic_write_around(APIC_LDR, apic_read(APIC_LDR));
Unfortunately, there is no single spot in the code identifying start and end of an interrupt, so I had to fish for all places where they were happening. I got it to work, and the balance is so fragile, that if I only touch any of those places it immediately breaks or hangs... I wish there were macros in place: irq_enter(), irq_exit() for IO-APIC irq's like in UnixWare, say.
I am sure there are people (especially from Intel, with red books newer than mine) who are looking into this or could shed more light on how this can be properly implemented.
--Natalie - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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