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SubjectRe: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell box
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The iTLB would be flushed when he did the reload of cr3 ( per your
suggestion ) UNLESS the G bit was set.
I suppose theres some small chance, that at the time this instruction was
first cached and its corresponding iTLB entry was loaded, the G bit may
have been set.. Seems unlikely. but I'll hack up something to
unconditionally flush the iTLB.

- jim

Alan Cox <alan@lxorguk.ukuu.org.uk>@vger.kernel.org on 03/20/2002 04:04:51
PM

Sent by: linux-kernel-owner@vger.kernel.org


To: kurt@garloff.de (Kurt Garloff)
cc: tepperly@llnl.gov (Tom Epperly), linux-kernel@vger.kernel.org (Linux
kernel list)
Subject: Re: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell
box



> disassembly?
> AFAICS, its a push %ebp instruction, which should not be illegal. So
either
> your stack is overflowing or my suspicion with the defect CPU is
applicable.

Or somehow the I/D TLB's got messed up and the ITLB for that entry is now
wrong.
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