Messages in this thread | | | Subject | Re: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell box | From | "James Washer" <> | Date | Wed, 20 Mar 2002 16:30:18 -0800 |
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The iTLB would be flushed when he did the reload of cr3 ( per your suggestion ) UNLESS the G bit was set. I suppose theres some small chance, that at the time this instruction was first cached and its corresponding iTLB entry was loaded, the G bit may have been set.. Seems unlikely. but I'll hack up something to unconditionally flush the iTLB.
- jim
Alan Cox <alan@lxorguk.ukuu.org.uk>@vger.kernel.org on 03/20/2002 04:04:51 PM
Sent by: linux-kernel-owner@vger.kernel.org
To: kurt@garloff.de (Kurt Garloff) cc: tepperly@llnl.gov (Tom Epperly), linux-kernel@vger.kernel.org (Linux kernel list) Subject: Re: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell box
> disassembly? > AFAICS, its a push %ebp instruction, which should not be illegal. So either > your stack is overflowing or my suspicion with the defect CPU is applicable.
Or somehow the I/D TLB's got messed up and the ITLB for that entry is now wrong. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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