Messages in this thread | | | From | "Jeff Merkey" <> | Subject | Fw: Performance counter and APIC | Date | Thu, 3 Jun 1999 15:58:02 -0600 |
| |
----- Original Message ----- From: Jeff Merkey <jmerkey@timpanogas.com> To: Guillaume Thouvenin <guill@casi.polymtl.ca> Sent: Thursday, June 03, 1999 3:38 PM Subject: Re: Performance counter and APIC
> Guillaume, > > I have already implemented full EMON code in MANOS (another open source OS) > as well as the APIC code. APIC doesn't really have a lot to do with EMON > stats -- EMON are performance counters that are internal in the processors. > I am sending you the code for the Pentium, Pentium Pro, and Pentium III > processors. I am also including an APIC module. You are required to post > this code back to me after you change it so I can get it rolled into Linux. I will send the code to you > directly as not to junk up the linux-kernel mailing list. > > Jeff > > P.S. > > Here's a sample of which types of things this code monitors for EMON. > Ignore the MANOS copyright -- this code is now under GPL. > > > /*************************************************************************** > * > * Copyright (c) 1997, 1998 Timpanogas Research Group, Inc. All Rights > * Reserved. > * > * This program is an unpublished work of TRG, Inc. and contains > * trade secrets and other proprietary information. Unauthorized > * use, copying, disclosure, or distribution of this file without the > * consent of TRG, Inc. can subject the offender to severe criminal > * and/or civil penalities. > * > * > * AUTHOR : Jeff V. Merkey > * FILE : MONITOR.C > * DESCRIP : Console Monitor for MANOS v1.0 > * DATE : January 10, 1998 > * > * > ***************************************************************************/ > > #include "stdarg.h" > #include "stdio.h" > #include "stdlib.h" > #include "ctype.h" > #include "string.h" > #include "kernel.h" > #include "keyboard.h" > #include "screen.h" > #include "types.h" > #include "emit.h" > #include "dos.h" > #include "tss.h" > #include "os.h" > #include "mps.h" > #include "hal.h" > #include "window.h" > #include "menu.h" > #include "dosfile.h" > #include "timer.h" > #include "peexe.h" > #include "line.h" > #include "loader.h" > #include "malloc.h" > #include "free.h" > #include "event.h" > > extern uint32 mpt_total_pages; > extern uint32 mpt_reserved_pages; > extern uint32 mpt_physical_pages; > extern uint32 mpt_logical_pages; > extern uint32 mpt_special_pages; > extern uint32 mpt_available_pages; > extern uint32 mpt_system_page_count; > extern uint32 mpt_system_page_use_count; > extern uint32 mpt_move_counter; > extern uint32 mpt_alloc_physical_count; > extern uint32 mpt_return_physical_count; > > extern LONG page_fault_success; > extern LONG page_fault_failure; > extern LONG page_fault_move_counter; > extern LONG page_fault_alloc_error; > extern LONG *mpt_physical_block_list_head; > extern LONG mpt_physical_block_activity; > extern LONG *mpt_system_list_head; > extern LONG mpt_system_page_activity; > extern LONG *mpt_list_head; > extern LONG *mpt_activity_counter; > > LONG last_mpt_move_counter; > LONG last_page_fault_success; > LONG last_page_fault_failure; > LONG last_page_fault_move_counter; > LONG last_page_fault_alloc_error; > LONG last_alloc_physical_count; > LONG last_return_physical_count; > LONG last_physical_block_count; > LONG last_physical_block_activity; > LONG last_system_page_count; > LONG last_system_page_activity; > LONG last_regular_page_count; > LONG last_regular_page_activity; > LONG mpt_regular_page_count; > LONG mpt_regular_page_activity; > > #define PENTIUM_EVENT 0x0011 > #define PENTIUM_COUNTER_1 0x0012 > #define PENTIUM_COUNTER_2 0x0013 > > #define PPII_COUNTER_1 0x00C1 > #define PPII_COUNTER_2 0x00C2 > #define PPII_EVENT_1 0x0186 > #define PPII_EVENT_2 0x0187 > > #define PENTIUM_PPII_STDC 0x0010 > > #define EMON_CALL 0x01C0 > #define EMON_C3 0x0180 > #define EMON_C3_NON 0x0140 > #define EMON_ALL 0x00C0 > #define EMON_R3 0x0080 > #define EMON_R3_NON 0x0040 > #define EMON_NONE 0x0000 > > LONG PreemptiveEvents = 0; > LONG PagingCount = 0; > LONG TotalInterrupts = 0; > LONG LockAssertions = 0; > LONG PageFaults = 0; > LONG TLBShootdowns = 0; > LONG TotalXCalls; > LONG XCallFailures; > LONG XCallBusyCount; > > LONG MonitorActive = 0; > LONG DaysUp = 0; > LONG HoursUp = 0; > LONG MinutesUp = 0; > LONG SecondsUp = 0; > LONG TicksUp = 0; > LONG UpdateStats = 0; > LONG EMONUpdateOK = 0; > > BYTE *kernelStateArray[]={ > "PS_INIT ", > "PS_ACTIVE", > "PS_SLEEP ", > "PS_SYNC ", > "PS_LWP ", > "PS_HALT ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? ", > " ????? " > }; > > BYTE *engineState[]={ > "INACTIVE", > "ACTIVE ", > "DEBUG ", > "SIGNAL ", > "FATAL ", > "INIT ", > "SHUTDOWN", > "RESUME ", > "LOCK ", > "CURRENT ", > "SUSPEND ", > "?????? ", > "?????? ", > "?????? ", > "?????? ", > "?????? ", > "?????? ", > "?????? ", > "?????? " > }; > > BYTE widgets[4]={ '|', '/', '-', '\\' }; > > LONG EMONClocks[MAX_PROCESSORS]; > LONG EMONCounter1[MAX_PROCESSORS]; > LONG EMONCounter2[MAX_PROCESSORS]; > LONG EMONRegisters[2] = { -1, -1 }; > LWP EMONLWP[MAX_PROCESSORS]; > LWP EMONLWPSet[MAX_PROCESSORS]; > > BYTE *PentiumEMON[]={ > "Data Read ", > "Data Write ", > "Data Read or Data Write ", > "Data Read Miss ", > "Data Write Miss ", > "Data Read Miss or Data Write Miss ", > "Data TLB Miss ", > "Write (hit) to M or E state lines ", > "Data Cache Lines Written Back ", > "Data Cache Snoops ", > "Data Cache Snoop Hits ", > "Memory Accesses In Both Pipes ", > "Bank Conflicts ", > "Misaligned Data Memory References ", > "Code Read ", > "Code TLB Miss ", > "Code Cache Miss ", > "Any Segment Register Load ", > "Branches ", > "BTB Hits ", > "Taken Branch or BTB Hit ", > "Pipeline Flushes ", > "Instructions Executed ", > "Instructions Executed in the v-pipe", > "Bus Utilization (clocks) ", > "Pipeline Stalled by Write Backup ", > "Pipeline Stalled by Data Mem Read ", > "Pentium Stalled by write to E or M ", > "Locked Bus Cycle ", > "I/O Read or Write Cycle ", > "Non-cacheable memory references ", > "AGI (Address Generation Interlock) ", > "Floating Point Operations ", > "Breakpoint 0 Match ", > "Breakpoint 1 Match ", > "Breakpoint 2 Match ", > "Breakpoint 3 Match ", > "Hardware Interrupts " > > > > }; > > BYTE *PentiumProEMON[]={ > "Violations of Strong Ordering Detected ", > "Number of Store Buffer Forwards ", > "Number of Store Buffer Blocks ", > "Number of Store Buffer Drain Cycles ", > "Misaligned Data References ", > "Segment Register Loads ", > "Floating Point Operations (0) ", > "Floating Point Exceptions ", > "Number of Multiplies (1) ", > "Number of Divides (1) ", > "Number Busy Divider Cycles (0) ", > "Number of L2 Address Strobes ", > "L2 Cache Data Bus Busy Cycles ", > "L2 Cache Data Bus Busy During Transfer ", > "L2 Cache Allocated Lines ", > "L2 Cache Allocated M State Lines ", > "L2 Cache Evicted Lines ", > "L2 Cache M State Evicted Lines ", > "L2 Cache Instruction Fetches ", > "L2 Cache Loads (Reads) ", > "L2 Cache Stores (Writes) ", > "L2 Cache Locks ", > "L2 Cache Data Requests ", > "L2 Cache Reads ", > "L2 Cache Requests ", > "L1 Cache Data Reads ", > "L1 Cache Data Writes ", > "L1 Cache Data Locks ", > "Data Memory References ", > "L1 Cache Data Requests ", > "Lines Brought Into L1 Cache ", > "L1 Cache Allocated M State Lines ", > "L1 Cache Evicted M State Lines ", > "L1 Data Cache Misses Outstanding ", > "Data TLB Misses ", > "Breakpoint Matches ", > "External Bus Requests Outstanding ", > "Bus Clock Cycles Driving BNR Pin ", > "Bus Clock Cycles Asserting DRDY ", > "Bus Clock Cycles with LOCK# Asserted ", > "Bus Clock Cycles During PROC Data Receive ", > "Bus Burst Read Transactions ", > "Bus Read for Ownership Transactions ", > "Bus WB or M State Lines Evicted/writeback ", > "Bus Burst Instruction Fetches ", > "Bus Invalidate Transactions ", > "Bus Partial Write Transactions ", > "Bus Partial Mem Transactions/MemMappedIO ", > "Bus IO Transactions (IN/OUT) ", > "Bus Deferred Reply Transactions ", > "Bus Burst Transactions ", > "Bus Memory Transactions ", > "Bus Transactions ", > "Burst Reads Snooped By L1 ", > "Invalidate Transactions Snooped by L1 ", > "Bus Requests Snooped by L1 ", > "Burst Reads Snooped by L1 and L2 ", > "Invalidates Snooped by L1 and L2 ", > "Bus Requests Snooped by L1 and L2 ", > "Snoop Responses to Transactions (ext bus) ", > "Number of Data Bus Stalls ", > "CPU Not Halted Cycles ", > "Number HIT pin Assertions ", > "Number HITM pin Assertions ", > "Number AERR pin Assertions ", > "Number BERR pin Assertions ", > "BINIT pin Assertions/Bus Snoop Stalls ", > "Instruction Fetches ", > "Instruction Fetch Misses ", > "Uncacheable Instruction Fetches ", > "Prefetch Hits ", > "Breakpoint Matches ", > "Instruction TLB Misses ", > "Cycles Instruction Fetch is Stalled ", > "Cycles Instruction Fetch is Stalled (pipe)", > "UOPs Dispatched from Resv. Stn ", > "Cycles during UOP Dispatch ", > "Resource Related Stalls ", > "Instructions Retired ", > "Floating Point Operations Retired (0) ", > "UOPs Retired ", > "Self Modifying Code Detected ", > "Branch Instructions Retired ", > "Branch Miss-Predictions Retired ", > "Clocks While Interrupts are Masked ", > "Clocks While Interrupts are Masked/Pending", > "Hardware Interrupts ", > "Taken Branches Retired ", > "Taken Mispredictions Retired ", > "Instructions Decoded ", > "OUPs Decoded ", > "Register Renaming (Partial) Stalls ", > "Cycles that Register Renaming Stalls Occur", > "Branch Instructions Decoded ", > "BTB Hits ", > "BTB Misses ", > "Return Stack Buffer Hits ", > "Bogus Branches Detected ", > "Mispredicted Returns Retired ", > "Number of BACLEARS# Asserted " > }; > > LONG PentiumEMONCodes[] = { > 0x00, 0x01, 0x28, 0x03, 0x04, 0x29, 0x02, 0x05, 0x06, 0x07, 0x08, 0x09, > 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, > 0x18, 0x19, 0x1A, 0x1B, 0x1C, 0x1D, 0x1E, 0x1F, 0x22, 0x23, 0x24, 0x25, > 0x26, 0x27 > }; > > LONG PentiumProEMONCodes[] = > { > 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x10, 0x11, 0x12, 0x13, 0x14, 0x21, > 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x2B, 0x2C, 0x2D, > 0x2E, 0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, > 0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x6B, > 0x6C, 0x6D, 0x6E, 0x6F, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, > 0x78, 0x79, 0x7A, 0x7B, 0x7C, 0x7D, 0x7E, 0x80, 0x81, 0x82, 0x83, 0x84, > 0x85, 0x86, 0x87, 0xA0, 0xA1, 0xA2, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, > 0xC6, 0xC7, 0xC8, 0xC9, 0xCa, 0xD0, 0xD1, 0xD2, 0xD3, 0xE0, 0xE1, 0xE2, > 0xE3, 0xE4, 0xE5, 0xE6 > }; > > extern LONG NumberOfOpenHandles; > extern LONG TotalSystemMemory; > extern LONG HighMemoryLength; > extern > > > ----- Original Message ----- > From: Guillaume Thouvenin <guill@casi.polymtl.ca> > To: <linux-kernel@vger.rutgers.edu> > Sent: Thursday, June 03, 1999 12:22 PM > Subject: Performance counter and APIC > > > > I would like to implement the management of performance counters > > interrupts on a Pentium Pro. I encounter the following problem: > > > > To manage the interrupt, I need to configure the APIC. The APIC seems > > to > > be used only in SMP mode, though. The problem is that I'm in > > mono-processor mode. Is it possible to use the APIC without choosing the > > SMP mode during the kernel configuration or is it possible to recover > > the counters interrupts without using the APIC at all? > > > > __________________________________ > > Guillaume Thouvenin > > mailto:guill@casi.polymtl.ca > > http://www.multimania.com/thouveni > > > > - > > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > > the body of a message to majordomo@vger.rutgers.edu > > Please read the FAQ at http://www.tux.org/lkml/ > > >
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.rutgers.edu Please read the FAQ at http://www.tux.org/lkml/
| |